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cy7c1020cv33 512 k (32 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05133 rev. *i revised october 4, 2013 512 k (32 k 16) static ram features pin- and function-compatible with cy7c1020cv33 temperature ranges ? commercial: 0 c to 70 c ? industrial: ?40 c to 85 c ? automotive: ?40 c to 125 c high speed ? t aa = 10 ns cmos for optimum speed/power low active power ? 325 mw (max) automatic power-down when deselected independent control of upper and lower bits available in pb-free and non pb-free 44-pin tsop ii package functional description the cy7c1020cv33 is a high-pe rformance cmos static ram organized as 32,768 words by 16 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 14 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 9 through i/o 16 ) is written into the location specified on the address pins (a 0 through a 14 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 1 to i/o 8 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 9 to i/o 16 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 1 through i/o 16 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1020cv33 is available in standard 44-pin tsop type ii package. 32k 16 ram array i/o 1 ?i/o 8 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 sense amps data in drivers oe a 2 a 1 i/o 9 ?i/o 16 ce we ble bhe a 8 logic block diagram
cy7c1020cv33 document number: 38-05133 rev. *i page 2 of 16 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 pin definitions .................................................................. 4 maximum ratings ............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 6 thermal resistance .......................................................... 6 ac test loads and waveforms ....................................... 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ......................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc? solutions ...................................................... 16 cypress developer community ................................. 16 technical support ................. .................................... 16
cy7c1020cv33 document number: 38-05133 rev. *i page 3 of 16 selection guide description -10 -12 -15 unit maximum access time 10 12 15 ns maximum operating current co mmercial/industrial 90 85 80 ma automotive ? ? 85 ma maximum cmos standby current commercial/industrial 5 5 5 ma automotive ? ? 10 ma pin configuration figure 1. 44-pin tsop type ii pinout (top view) [1] we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view tsop ii 12 13 41 44 43 42 16 15 29 30 v cc a 14 a 13 a 12 nc nc a 3 oe v ss a 5 i/o 16 a 2 ce i/o 3 i/o 1 i/o 2 bhe nc a 1 a 0 18 17 20 19 i/o 4 27 28 25 26 22 21 23 24 nc v ss i/o 7 i/o 5 i/o 6 i/o 8 a 6 a 7 ble v cc i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 a 8 a 9 a 10 a 11 a 4 note 1. nc pins are not connected on the die.
cy7c1020cv33 document number: 38-05133 rev. *i page 4 of 16 pin definitions pin name pin number i/o type description a 0 ?a 14 5, 4, 3, 2, 18, 44, 43, 42, 27, 26, 25, 24, 21, 20, 19 input address inputs used to select one of the address locations . i/o 1 ?i/o 16 7?10, 13?16, 29?32, 35?38 input/output bidirectional data i/o lines . used as input or output lines depending on operation. nc 1, 22, 23, 28 no connect no connects . not connected to the die. we 17 input/control write enable input, active low . when selected low, a write is conducted. when deselected high, a read is conducted. ce 6 input/control chip enable input, active low . when low, selects the chip. when high, deselects the chip. bhe , ble 40, 39 input/control byte write select inputs, active low . bhe controls i/o 16 ?i/o 9 , ble controls i/o 8 ?i/o 1 . oe 41 input/control output enable, active low . controls the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. v ss 12, 34 ground ground for the device . should be connected to ground of the system. v cc 11, 33 power supply power supply inputs to the device.
cy7c1020cv33 document number: 38-05133 rev. *i page 5 of 16 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [2] ................................?0.5 v to +4.6 v dc voltage applied to outputs in high z state [2] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 3.3 v ? 10% industrial ?40 ? c to +85 ? c 3.3 v ? 10% automotive ?40 ? c to +125 ? c 3.3 v ? 10% electrical characteristics over the operating range parameter description test conditions -10 -12 -15 unit min max min max min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? 2.4 ? 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ?0.4?0.4?0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [2] ? 0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc commercial / industrial ? 1+1?1+1?1+1 ? a automotive ? ? ? ? ?20 +20 ? a i oz output leakage current gnd < v i < v cc , output disabled commercial / industrial ? 1+1?1+1?1+1 ? a automotive ? ? ? ? ?20 +20 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc commercial / industrial ?90?85?80ma automotive ? ? ? ? ? 85 ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max commercial / industrial ?15?15?15ma automotive ? ? ? ? ? 20 ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 commercial / industrial ?5?5?5ma automotive ? ? ? ? ? 10 ma note 2. v il (min) = ?2.0 v and v ih (max) = v cc + 0.5 v for pulse durations of less than 20 ns.
cy7c1020cv33 document number: 38-05133 rev. *i page 6 of 16 capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 8 pf c out output capacitance 8pf thermal resistance parameter [3] description test conditions 44-pin tsop-ii unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 76.92 ? c/w ? jc thermal resistance (junction to case) 15.86 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 30 pf r 317 ? r2 351 ? rise time: 1 v/ns fall time: 1 v/ns (b) (a) 3.3 v output 5 pf (c) r 317 ? r2 351 ? high z characteristics: notes 3. tested initially and after any design or process changes that may affect these parameters. 4. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v.
cy7c1020cv33 document number: 38-05133 rev. *i page 7 of 16 switching characteristics over the operating range parameter [5] description -10 -12 -15 unit min max min max min max read cycle t rc read cycle time 10 ? 12 ? 15 ? ns t aa address to data valid ? 10 ? 12 ? 15 ns t oha data hold from address change 3 ? 3 ? 3 ? ns t ace ce low to data valid ? 10 ? 12 ? 15 ns t doe oe low to data valid ? 5 ? 6 ? 7 ns t lzoe oe low to low z [6] 0? 0 ? 0 ? ns t hzoe oe high to high z [6, 7] ?5 ? 6 ? 7 ns t lzce ce low to low z [6] 3? 3 ? 3 ? ns t hzce ce high to high z [6, 7] ?5 ? 6 ? 7 ns t pu [8] ce low to power-up 0 ? 0 ? 0 ? ns t pd [8] ce high to power-down ? 10 ? 12 ? 15 ns t dbe byte enable to data valid ? 5 ? 6 ? 7 ns t lzbe byte enable to low z 0 ? 0 ? 0 ? ns t hzbe byte disable to high z ? 5 ? 6 ? 7 ns write cycle [9] t wc write cycle time 10 ? 12 ? 15 ? ns t sce ce low to write end 8 ? 9 ? 10 ? ns t aw address set-up to write end 7 ? 8 ? 10 ? ns t ha address hold from write end 0 ? 0 ? 0 ? ns t sa address set-up to write start 0 ? 0 ? 0 ? ns t pwe we pulse width 7 ? 8 ? 10 ? ns t sd data set-up to write end 5 ? 6 ? 8 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t lzwe we high to low z [6] 3? 3 ? 3 ? ns t hzwe we low to high z [6, 7] ?5 ? 6 ? 7 ns t bw byte enable to end of write 7 ? 8 ? 9 ? ns notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (c) of ac test loads. transition is measured ?? 500 mv from steady-state voltage. 8. this parameter is guaranteed by design and is not tested. 9. the internal write time of the memory is defined by the overlap of ce low, we low and bhe /ble low. ce , we and bhe /ble must be low to initiate a write, and the transition of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
cy7c1020cv33 document number: 38-05133 rev. *i page 8 of 16 switching waveforms figure 3. read cycle no. 1 [10, 11] figure 4. read cycle no. 2 (oe controlled) [11, 12] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb notes 10. device is continuously selected. oe , ce , bhe and/or bhe = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low.
cy7c1020cv33 document number: 38-05133 rev. *i page 9 of 16 figure 5. write cycle no. 1 (ce controlled) [13, 14] figure 6. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble t t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce notes 13. data i/o is high impedance if oe or bhe and/or ble = v ih . 14. if ce goes high simultaneously with we going high, the output remains in a high-impedance state.
cy7c1020cv33 document number: 38-05133 rev. *i page 10 of 16 figure 7. write cycle no. 3 (we controlled, oe low) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe
cy7c1020cv33 document number: 38-05133 rev. *i page 11 of 16 truth table ce oe we ble bhe i/o 1 ?i/o 8 i/o 9 ?i/o 16 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high z read ? lower bits only active (i cc ) h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high z write ? lower bits only active (i cc ) h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc )
cy7c1020cv33 document number: 38-05133 rev. *i page 12 of 16 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 15 CY7C1020CV33-15ZSXE 51-85087 44-pin tsop type ii (pb-free) automotive CY7C1020CV33-15ZSXEt 51-850 87 44-pin tsop type ii (pb-free) automotive x = t or blank t = tape and reel; blank = tube temperature range: e = automotive pb-free package type: zs = 44-pin tsop type ii speed grade: 15 ns v33 = 3.3 v process technology ? 0.16 m part identifier technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c 1020 c - 15 zs e v33 x cy 7 x
cy7c1020cv33 document number: 38-05133 rev. *i page 13 of 16 package diagrams figure 8. 44-pin tsop z44-ii package outline, 51-85087 51-85087 *e
cy7c1020cv33 document number: 38-05133 rev. *i page 14 of 16 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tsop thin small-outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mw milliwatt ns nanosecond % percent pf picofarad vvolt wwatt
cy7c1020cv33 document number: 38-05133 rev. *i page 15 of 16 document history page document title: cy7c1020cv33, 512 k (32 k 16) static ram document number: 38-05133 rev. ecn no. issue date orig. of change description of change ** 109428 12/16/01 hgk new data sheet. *a 115045 05/30/02 hgk i cc and i sb1 data modified *b 117615 08/14/02 dfp pin 1= nc pin 18 = a4; remove soj package option; remove 8ns option. *c 262949 see ecn rkf added automotive specs to data sheet *d 334398 see ecn syt added lead-free product information *e 493543 see ecn nxr added note #1 on page #1 changed the description of i ix from input load current to input leakage current in dc electrical characteristics table removed i os parameter from dc electrical characteristics table updated ordering information table *f 2897691 03/23/2010 rame updated ordering information updated package diagrams . *g 3057593 10/13/2010 pras updated ordering information and added ordering code definitions . *h 3100106 12/02/2010 pras added acronyms and units of measure . minor edits and updated in new template. *i 4146968 10/04/2013 vini updated package diagrams : spec 51-85087 ? changed revision from *c to *e. updated in new template. completing sunset review.
document number: 38-05133 rev. *i revised october 4, 2013 page 16 of 16 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1020cv33 ? cypress semiconductor corporation, 2001-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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